Vias are known in the art as structures that may be used to electrically connect a lower conductive structure such as a contact, pad, layer, or pattern to an upper conductive structure such as a contact, pad, layer, or pattern that is vertically separated from the lower conductive structure. Vias typically penetrate vertically through one or more horizontally arranged structural layers that separate the lower conductive structure and the upper conductive structure.
MRAM devices are also known. For purposes of this disclosure, a complete and thorough discussion of the structure and workings of an MRAM device is not necessary, as the basic knowledge of these devices possessed by those of skill in the art is sufficient for understanding the inventive aspects that are discussed below in the detailed description of example embodiments.
Vias have frequently been used to electrically connect a local interconnect layer with the top electrode of an MRAM memory bit. In order to reduce the cost and improve the performance of the MRAM device, it has been proposed that, rather than connect the local interconnect layer to the top electrode of the MRAM memory bit using a via, the top electrode of the MRAM memory bit might instead directly contact the local interconnect. This can be accomplished through the planarization of deposited dielectric to the top of the top electrode.
After the planarization of the dielectric to the top of the top electrode, a contact metal layer is typically deposited on the top electrode of the MRAM memory bit and the surrounding dielectric. The deposition of the contact metal layer over the top electrode creates an opaque, reflective surface that can not be aligned. That is, the surface of the contact metal layer does not provide clues or indications as to where the underlying top electrode is positioned, making it impossible to align subsequent layers that must have a specific geometry relative to the top electrode. To solve this problem, a photo lithography mask and etch steps are performed on top of the contact metal layer to form a key. The key can then be used to properly align the contact metal layer.
FIG. 1 is a cross-sectional diagram illustrating a MRAM device where the top electrode 102 of the MRAM memory bit is connected to the local interconnect 104 using a via 106, while FIG. 2 is a cross-sectional diagram illustrating a MRAM device where the top electrode 102 of a MRAM memory bit is connected directly to the local interconnect 104. Compared to FIG. 1, it can be seen that the MRAM device of FIG. 2 does not require a deposition process such as a chemical vapor deposition (CVD) process to add the layer 108 of FIG. 1. The MRAM device of FIG. 2 additionally eliminates a cleaning process, a photo mask process, and an etch process that would otherwise be needed to create the spaces that are needed for the vias 106 of FIG. 1.
In addition to the benefit of reduced cost, the elimination of layer 108 in FIG. 2 brings the upper write line 110 closer to the top electrode 102, which improves the functionality of the MRAM device by reducing the current required to switch the memory state of the device.
While the structure illustrated in FIG. 2 can achieve reduced cost and improved functionality, it is offset by the fact that elimination of the vias still requires a key photolithography mask and etching process on the contact metal layer for proper alignment, as was explained above. Embodiments of the invention address this and other disadvantages of the conventional art.